...using "EMIB"? What happened to make this possible now versus previously? Is this some technology innovation? A business decision driven by management with a different perspective, making different trade-offs (ie sacrifice product cost for more variety/time to market?), or some manufacturing innovation?
It sounds like a good idea, so why now and not 5 years ago or 2 years ago? What's changed?
-1aqf -- I see that. I think that's been conventional intel thinking for long time. So why make the move now? What changed?
While nice from a packaging point of view, it makes life difficult from a silicon support point of view. Every process wants its own specific voltage(s) resulting in an explosion of the Package surrounding VRDs. Even when they have a common voltage, they want it to be sequenced on in a specific order. Even clocks need to be gated on at different times. Then there is the headache of accommodating the signaling voltage between two pieces of different silicon. While the idea of mixing different silicon functions in the same package is seductive, every silicon combination needs to be validated. The majority of the cost of getting a "solution" "shipment ready" is spent in validation and verification. To justify the cost, the silicon combination needs to have a healthy ROI, which should include a recall contingency cost, as the more independent silicon pieces you put together the bigger the risk of having a validation miss.
In the last 10 years Intel has fallen behind with their inward fascination of leadership.
The smartphone and foundry went from being far in their distant rear view mirror to along side this year to passing them by next year.
Case study in technology arrogance ruining a company 😂
Easier to yield multiple small dies than one large due. Also you can mix and match technologies, not all circuits need to be on the latest process node.
http://www.anandtech.com/show/11183/amd-prepares-32-core-naples-cpus-for-1p-and-2p-servers-coming-in-q2
While not specifically mentioned in the announcement today, we do know that Naples is not a single monolithic die on the order of 500mm2 or up. Naples uses four of AMD’s Zeppelin dies (the Ryzen dies) in a single package. With each Zeppelin die coming in at 195.2mm2, if it were a monolithic die, that means a total of 780mm2 of silicon, and around 19.2 billion transistors. Yield is an answer.
Why ask on a layoff board of all places?
Ask on Anandtech's forum......
TSMC already shipping multi-die packaging for revenue using INFO and CoWas. Intel late again - no surprise.
That is IP.