Thread regarding Intel Corp. layoffs

Yields tend to go up non linearly at first because when a problem is solved it is a dramatic increase in overall yield, as the node matures, yield increases become incremental fine tuning. Intel is adding 3 new technologies at once GAA, Ultra EUV and Power VIA IIRC. Setting the parameters correctly will see large jumps in yields at first, it's normal.

Right now there is no gating path to tune yields to 65%. Beyond that may be a lot harder as it becomes very small adjustments and trade offs.

So let's say you are correct and it's that high now (35% unlikely).

In three months through various holiday periods the yield will gain 30%... hmm... Not sure that math is mathing with how improvements tend to work.

More likely that daddy gov pushes some 3rd parties to provide handouts that float the debt and minimize more massive layoffs.

While it struggles to generate profit and get a customer. 6 months left.

@cs In general your statement is correct. But, fortunately, the 18A process has a huge performance margin. At the initial stage of process development, specifications define leakage as a critical yield parameter, while the chip speed with GAA and PowerVIA is clearly superior to any other chips, which are using today previous processes. Chip speed and leakage are inversely correlated, and process engineers always have some process ability to fine-tune leakage at the expense of some degradation in chip speed (per need). Since the leakage (unlike performance) can be relatively easily controlled and monitored in electrical test inline, the yield related to leakage is generally not an issue.

Ya….delay delay, a few quarters for sure, no worries, delay, delay…,,,,,,

Intel liars. I don’t believe it can archive 30% another decade. It stuck at 14nm for decade before. What did it have at 10nm 7nm 5nm 3nm with its own design? Moore is dead so Intel are liars now.

@b7 While I'm not an engineer, I would add in addition to die size, defect density, and chip complexity (CPU, GPU, memory, etc)... there is also leakage and performance metrics. You can get a functioning die off a wafer, but if it doesn't meet performance or power specs, it's basically non-salable.

Says the guy from Intel. Always lies and bullsh-t.

There are different size test dies.

Things that are outside your limited zones of knowledge is not "illiterate". Are you a re--rd?

@bg Small test die? What does this illiterate nonsense mean? Test chip X78 is not small. Its area for Intel is always about the same within the same technology from the very first day of 18A technology. But it is completely different from what TSMC and Samsung use. Test chip has multiple structures on it and it finally measures defect density EOL and defines type of defect.

That's where it's at for small test dies. If you know a different answer, keep it to yourself and feel like the "special" person you are. This is a forum, you can share or you can choose not to.

Yep. The percentage of good chips depends on the chip area, the content with different print densities (CPU, GPU, or SRAM, etc.), and the defect density. Logic, GPUs, and memory on the same process will demonstrate different yields for the same chip size. Therefore, comparing yield percentages for different products is meaningless. Either defect density or RISO (for similar products) is used in semiconductors.

Fishing? You have missed the yield numbers. Try again.