Thread regarding Intel Corp. layoffs

Ok we had 2400, but shouldn't there be another 2000 in oregon?

Cause the numbers doesn't add up

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| 3675 views | | 18 replies (last July 17) | Reply
Post ID: @OP+1jzzp831j

18 replies (most recent on top)

@et: kids and former Intel going to PCC

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Post ID: @y1+1jzzp831j

@km Do mean like what they used to do at D1C before they de decided that high production superseded all things because it was the only way to go? Back when they actually met production goals? It’s said that a company will fail five years after giving up R&D and/or training. Intel did both 12 years ago. Enter 14 nm saga. So, here we are. Any real training or R&D getting done effectively?

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Post ID: @kx+1jzzp831j

@k9 Oh, I didn't say what they handed to HVM was perfect, or even passable in many cases.

TD has long considered that when they can produce 1 functioning die, that the process is ready for HVM.

No, the perfectionism is about TD process engineers and tool owners micromanaging the tools and recipes to an extent which merely adds complexity and needless degrees of uniqueness to how the factory operates. The result is far from perfect, but it is caused by perfectionism.

TSMC does not operate like this and the easiest way to stop it is to put TD in their own, small fab and let them play with their toys and think they are engineering.

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Post ID: @km+1jzzp831j

Intel will keep updating the WARN numbers as more people are notified.

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Post ID: @kk+1jzzp831j

@jz Perfectionism? Everything TD passes off to HVM is half-baked at best. If TD were perfectionists they’d actually create documentation and wouldn’t just pass off half-assed and out of date BKMs as “specs”. HVM cleaning up after TD and is where a lot of the efficiency is lost in our manufacturing systems.

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Post ID: @k9+1jzzp831j

@hn The relative importance of R&D work has to be balanced with output cost.

TD has used the R&D excuse to take over fab production at Ronler and that has driven up wafer cost.

It was not always this way. Sohail effected this change as part of his empire building, and like most everything else he did this also needs to be scrapped. TD historically always had the smallest capacity fab, either entirely to themselves or lightly shared.

That way all the perfectionism they felt they needed did not have an impact on HVM wafer cost, even when copy-exactly was still rigidly enforced.

TD needs to go back to that model and may have to anyway as R&D cost is brought back in line with that of a typical foundry.

IDM allowed ProdCo profits to be used for TD, and that led to the endless complexity of TD org. True, BS went crazy with buybacks but that was because of how poorly the R&D investment was paying off. And that was because TD was and remains a managerial bag of snakes.

What I'm certain LBT will enforce going forward is R&D that is cost effective and leads to sellable product. TD has never operated within those boundaries and likely layers of management structure and complexity will be removed along the way.

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Post ID: @jz+1jzzp831j

@g1 you are aware TD does lot of important work right? They actually have the best techs, the techs on the manufacturing side aren't even that smart nor on par with those techs.

There is a reason why TD techs are better than production techs, even the engineer's are better on TD. Gotta ask what is manufacturing doing wrong with all those multiple managers who just sits there?

Intel is far behind technology, their greed of not investing more in RnD had led to its on downfall. Look at even other techs companies how much they are investing in RnD, Intel is just building fabs instead of hearing news about Intel trying to get better engineer's for RnD(but we hear this about other companies, countless articles saying XYC company paying this much to hire engineers)

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Post ID: @hn+1jzzp831j

@et I'm waiting for a housing crash so I can finally buy a house.

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Post ID: @gn+1jzzp831j

@ar would just be nice if TD would at least schedule tool time like they’re supposed to before running experiment lots in the middle of a weekend night that crash 5 separate tools at once because they forgot to update some parameter or ignore E3… then won’t answer their phones to help clean up their own messes, or at least explain. So much time wasted.

If they get their own tools they’ll end up taking the best techs from Foundry to be their Equipment Techs just like always.

There’s no winning. TD needs to be a paying customer and get treated like one, not like they’re running the show.

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Post ID: @g1+1jzzp831j

There goes Washington and Multnomah county housing, tax base and all the kids going to OSU instead of some private U

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Post ID: @et+1jzzp831j

It ain’t over

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Post ID: @e4+1jzzp831j

I agree, the total head count will be around 60K for Intel. This is just the first round. There are literally thousands of engineers looking for work here in Oregon. Either get into the trades or start a construction company.

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Post ID: @bn+1jzzp831j

The numbers can't go much higher, because there are only so many technicians to terminate.

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Post ID: @bh+1jzzp831j

Com on ….. there will be more!!! There will be blood!!!

What do you think…. They will keep all the MBAs???

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Post ID: @aw+1jzzp831j

Most of the layoffs are in OR, due to the need to right-size TD and the fabs.

But that total isn't likely to get over 4k. It's mostly done and reported at this point.

Notice how relatively small the reductions are at the other sites? They did not get as overstaffed for 18A.

Hopefully IFS will come up with a better fab model than having TD produce wafers. Go back to giving them something like D1C or D1D and sepearate that from HVM. This has been an unmitigated fiasco with regards to cost.

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Post ID: @ar+1jzzp831j

The WARN site DB didn’t have enough rows

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Post ID: @aq+1jzzp831j

This is just the start.

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Post ID: @aa+1jzzp831j

The WARN site updates numbers as they process notices, not when they are filed. That's why the Friday numbers were "delayed". I would not be surprised if there were a couple hundred more by next week.

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Post ID: @a1+1jzzp831j

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