Thread regarding Intel Corp. layoffs

Wow, Intel's first contra-process shrink.

BK,Murthy and others in the chain, are responsible for decimating Intel's engineering,design,manufacturing capabilities to the point the re-form factor from 10nm to 12nm will be highly difficult to execute. How is Intel filling it's commitments and planned orders without a stable manufacturing and logistics capability?

BK dumping stock wasn't about a security flaw, as a former manufacturing leader, he seems to have had visibility into the mess 10nm was shaping up to be.

Going from Intel going 10nm >> 12nm !. That's like you going to the grocery and buying a product that's the same size as before., with a few onces of product added to the same size package.

Samsung is building chips based on it's 8nm manufacturing process and delivering those chips to it's customers.

Whoa. Let's say Charlie is right - and then @1irt calls it well - we're at minimum a year+ and probably two for the next gen process - and even then, Intel will truly be BEHIND TSMC, GF and Samsung, with no clear path to catch up.

I am so happy I didn't have to pitch that tired old Tick-Tock process slide these last two years.

So now this has basically become just a 14nm shrink? Trading off density for yield is probably the right call, but it should have been done long ago. Looks like SemiAccurate was mostly accurate!

The speculation is the following:

• SAQP will go to SADP

• Cobalt will go back to copper

• Contact over active gate is gone

If this is true it implies that there will have to be new standard cell libraries with new timing models, new RC extraction tech files for the new wire delays, new SRAM bit cells and associated memory compilers, etc. The RTL would need to be updated to help close timing requiring new verification. The physical design would have to be started from scratch from floorplan, P/G, clocking, etc. All blocks with PnR would need to be respun, timing closure, EM/IR, LVS/DRC, etc. The packaging work would have to start from scratch.

Assuming these proposed changes happened recently we're looking at a minimum of eight months of physical design work before tape-out. Give two months in the fab for silicon. Then bring-up, debug, and +2 months for each stepping. We would normally allow around year after silicon for qualification. If you add all this up there's no way Intel can get 10nm product "on the shelves by the holidays" as promised in the conference call.

So it's like the Samsung 8 nm?,,, wonder which one will be in mass production first.