There is no CTO anymore. He's re-retired.
WD's ISA is for 32-bit in-order design with a 2-way superscalar architecture and a 9-stage pipeline- supposedly they want to use it for controllers (ssd and hdd?). never was clear who would make the silicon, though. While they mention AI, IoT, ML, etc., WD's design appears pretty low scale (i.e. can't touch tensor cores). I thought the memory coherency over ethernet fabric was more interesting myself- though again, nothing to get excited about from pure computing.
Martin apparently never really understood what a 'von Neumann architecture' is- confused by implementation compared to theory. Which, i guess, led to his push at HPE about 'the Machine' which was abandoned less than a year after he 'retired'. I assume he's really talking about the 'von Neumann bottleneck', but RISC doesn't address that. More buses to main memory would.
As for the CTO group- well, they appeared to have eliminated everything other than MRAM type memory. In theory, this should be in WD's wheelhouse, but it will come down to critical mass which the group doesn't have. Essentially trying to play catch-up w/ the competition.